View W332M72V-133SBI_6800958.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com general description the 256mbyte (2gb) sdram is a high-speed cmos, dy nam ic ran dom-access, memory using 5 chips containing 536,870,912 bits. each chip is internally con? gured as a quad-bank dram with a syn chro nous interface. each of the chips 134,217,728-bit banks is or ga nized as 8,192 rows by 1,024 columns by 16 bits. read and write accesses to the sdram are burst ori- ented; ac cess es start at a selected location and continue for a pro grammed number of locations in a programmed se quence. ac cess es be gin with the registration of an active com mand, which is then fol lowed by a read or write com mand. the address bits reg is tered coincident with the ac tive command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0- 12 select the row). the address bits reg is tered co in ci dent with the read or write com mand are used to se lect the starting col umn lo ca tion for the burst ac cess. the sdram provides for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be en abled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 2gb sdram uses an internal pipelined architecture to achieve high-speed operation. this architecture is com pat i ble with the 2n rule of pref etch architectures, but it also allows the column ad dress to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while ac cess ing one of the other three banks will hide the precharge cycles and provide seam less, high- speed, random-access op er a tion. the 2gb sdram is designed to operate at 3.3v. an auto refresh mode is provided, along with a power-saving, power-down mode. 32mx72 synchronous dram features high frequency = 100, 125, 133mhz package: ? 219 plastic ball grid array (pbga), 32 x 25mm 3.3v 0.3v power supply fully synchronous; all signals registered on pos i tive edge of system clock cycle internal pipelined operation; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst length 1,2,4,8 or full page 8,192 refresh cycles commercial, industrial and military temperature rang es organized as 32m x 72 weight: w332m72v-xbx C 3.5 grams typical benefits 40% space sav ings re duced part count re duced i/o count ? 19% i/o re duc tion re duced trace lengths for low er par a sit ic ca pac i tance suit able for hi-re li abil i ty ap pli ca tions lam i nate in ter pos er for op ti mum tce match pinout compatible with lower desities wedpn4m72v-xb2x, wedpn8m72v-xb2x and wedpn16m72v-xb2x * this product is subject to change without notice. discrete approach actual size s a v i n g s area 5 x 265mm 2 = 1328mm 2 800mm 2 40% i/o 5 x 54 pins = 270 pins 219 balls 19% count 25 32 11.9 11.9 11.9 11.9 11.9 22.3 54 tsop 54 tsop 54 tsop 54 tsop 54 tsop white electronic designs w332m72v-xbx
2 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com figure 1 C pin configuration note: dnu = do not use; to be left unconnected for future upgrades. nc = not connected internally. t op v iew 1 2345678910111213141516 a b c d e f g h j k l m n p r t dq 1 dq 3 dq 6 dq 7 cas 0 # cs 0 # v ss v ss nc nc dq 56 dq 57 dq 60 dq 62 vss v ss dq 30 dq 28 dq 25 dq 24 clk 1 cke 1 v cc v cc cs 2 # cas 2 # dq 39 dq 38 dq 35 dq 33 v cc dq 0 dq 2 dq 4 dq 5 dqml 0 we 0 # ras 0 # v ss v ss cke 3 clk 3 dqmh3 dq 58 dq 59 dq 61 dq 63 dq 31 dq 29 dq 27 dq 26 nc dqmh1 nc v ccq v ccq ras 2 # we 2 # dqml2 dq 37 dq 36 dq 34 dq 32 dq 14 dq 12 dq 10 dq 8 v cc v cc v cc v cc v cc v cc v cc v cc dq 55 dq 53 dq 51 dq 49 dq 17 dq 19 dq 21 dq 23 v ss v ss v ss vss v ss v ss v ss v ss dq 40 dq 42 dq 44 dq 46 dq 15 dq 13 dq 11 dq 9 dqmh0 clk 0 cke 0 v ccq v ccq cs 3 # cas 3 # we 3# dq 54 dq 52 dq 50 dq 48 dq 16 dq 18 dq 20 dq 22 dqml1 we 1 # cs 1 # v ss v ss cke 2 clk 2 dqmh2 dq 41 dq 43 dq 45 dq 47 v ss v ss v cc v ccq dnu dnu nc v ss v ss dnu ras 3 # dqml3 nc v ss v cc v ccq v ccq v cc v ss v ss nc ras 1 # cas 1 # v cc v cc nc dnu cs 4 # nc v cc v ss v ss a 9 a 0 a 2 a 12 nc dqmh4 dq 73 dq 75 dq 77 dq 79 a 8 a 1 a 3 dnu dnu we 4 # dq 70 dq 68 dq 66 dq 64 a 10 a 7 a 5 dnu ba 0 clk 4 dq 72 dq 74 dq 76 dq 78 a 11 a 6 a 4 dnu ba 1 cas 4 # dq 71 dq 69 dq 67 dq 65 v ss v ss v cc v ccq nc cke 4 nc v ss v cc v ccq v ccq v cc v ss v ss nc ras 4 # dqml4 v cc v ss v ss
3 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com a 0-12 a 0-12 ba 0-1 ba 0-1 clk 0 clk cas# dq 0 dq 15 cke 0 cke cs 0 # cs# dqml 0 dqml dqmh 0 dqmh ras 1 # we 1 # cas 1 # dq 0 dq 15 we# u1 ras# a 0-12 ba 0-1 clk 1 clk cas# dq 16 dq 31 ras 0 # we 0 # cas 0 # dq 0 dq 15 we# u0 ras# cke 1 cke cs 1 # cs# dqml 1 dqml dqmh 1 dqmh ras 2 # we 2 # cas 2 # dq 0 dq 15 we# u2 ras# a 0-12 ba 0-1 clk 2 clk cas# dq 32 dq 47 cke 2 cke cs 2 # cs# dqml 2 dqml dqmh 2 dqmh ras 3 # we 3 # cas 3 # dq 0 dq 15 we# u3 ras# a 0-12 ba 0-1 clk 3 clk cas# dq 48 dq 63 cke 3 cke cs 3 # cs# dqml 3 dqml dqmh 3 dqmh ras 4 # we 4 # cas 4 # dq 0 dq 15 we# u4 ras# a 0-12 ba 0-1 clk 4 clk cas# dq 64 dq 79 cke 4 cke cs 4 # cs# dqml 4 dqml dqmh 4 dqmh figure. 2 C functional block diagram
4 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to de? ne the speci? c mode of op er a tion of the sdram. this de? nition includes the selec-tion of a burst length, a burst type, a cas latency, an op er at ing mode and a write burst mode, as shown in figure 3. the mode register is programmed via the load mode reg is ter command and will retain the stored in for ma tion until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 spec i ? es the type of burst (sequential or in ter leaved), m4-m6 specify the cas latency, m7 and m8 specify the op er at ing mode, m9 spec i ? es the write burst mode, and m10 and m11 are reserved for future use. address a12 (m12) is unde? ned but should be driven low during loading of the mode register. the mode register must be loaded when all banks are idle, and the controller must wait the speci? ed time before ini ti at ing the subsequent operation. violating either of these requirements will result in unspeci? ed operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in fig ure 3. the burst length determines the maximum number of column lo ca tions that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are avail able for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown op er a tion or incompatibility with future versions may result. when a read or write command is issued, a block of col umns equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-9 when the burst length is set to two; by a2-9 when the burst length is set to four; and by a3-9 when the burst length is set to eight. the remaining (least signi? cant) all inputs and outputs are lvttl compatible. sdrams offer sub stan tial ad vanc es in dram op er at ing per for mance, in clud ing the ability to syn chro nous ly burst data at a high data rate with au to mat ic column-ad dress gen er a tion, the ability to in ter leave be tween in ter nal banks in order to hide precharge time and the capability to ran dom ly change col umn ad dress es on each clock cy cle dur ing a burst ac cess. functional de scrip tion read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a pro grammed number of locations in a pro grammed se quence. ac cess es begin with the registration of an active com mand which is then followed by a read or write com mand. the address bits registered coincident with the ac tive command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0-12 select the row). the address bits (a0-9) reg is tered coincident with the read or write com mand are used to select the start ing column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information cov er ing device initialization, register de? nition, command de scrip tions and de vice operation. initialization sdrams must be pow ered up and initialized in a pre de? ned manner. operational pro ce dures other than those spec i ? ed may result in unde? ned operation. once power is ap plied to v cc and v ccq (si mul ta neous ly) and the clock is stable (stable clock is de ? ned as a signal cycling within tim ing constraints specified for the clock pin), the sdram re quires a 100s delay prior to issuing any command other than a command inhibit or a nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop com mands should be applied. once the 100s delay has been satis? ed with at least one com mand inhibit or nop command having been ap plied, a precharge command should be applied. all banks must be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be per formed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. be cause the mode register will power up in an unknown
5 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com table 1 C burst definition burst length starting column address order of accesses within a burst type = sequential type = in ter leaved 2 a0 0 0-1 0-1 1 1-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a 0 -9 (location 0-y) cn, cn + 1, cn + 2 cn + 3, cn + 4... cn - 1, cn not supported figure 3 C mode register definition notes: 1. for full-page accesses: y = 1,024. 2. for a burst length of two, a1-9 select the block-of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-9 select the block-of-four burst; a0-1 select the starting column within the block. 4. for a burst length of eight, a3-9 select the block-of-eight burst; a0-2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-9 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-9 select the unique column to be accessed, and mode register bit m3 is ignored. m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a 9 a 7 a 6 a 5 a 4 a 3 a 8 a 2 a 1 a 0 mode register (mx) address bus m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a 10 a 11 reserved* reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = 0, 0 to ensure compatibility with future devices. a 12
6 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com figure 4 C cas latency operating mode the nor mal operating mode is selected by setting m7and m8 to zero; the other combinations of values for m7 and m8 are re served for future use and/or test modes. the pro grammed burst length applies to both read and write bursts. test modes and reserved states should not be used be cause unknown operation or incompatibility with future versions may result. table 2 C cas latency speed allowable operating frequency (mhz) cas latency = 2 cas latency = 3 -100 75 100 -125 100 125 -133 100 133 write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. clk command i/o clk command i/o t0 t1 t2 t3 t0 t1 t2 t3 t4 read nop nop cas latency = 2 d out t lz t oh t ac read nop nop nop d out t lz t oh t ac cas latency = 3 don't care undefined burst type accesses within a given burst may be pro grammed to be either se quen tial or interleaved; this is re ferred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is de ter mined by the burst length, the burst type and the start ing column address, as shown in table 1. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the avail abil i ty of the ? rst piece of output data. the latency can be set to two or three clocks. if a read command is registered at cloc k edge n, and the latency is m clocks, the data will be available by clock edge n+m. the i/os will start driving as a result of the clock edge one cycle ear li er (n + m - 1), and provided that the rel e vant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is pro grammed to two clocks, the i/os will start driving after t1 and the data will be valid by t2. table 2 below indicates the op er at ing fre quen cies at which each cas latency setting can be used. reserved states should not be used as unknown op er a tion or incompatibility with future versions may result.
7 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com truth table - commands and dqm operation (note 1) name (function) cs# ras# cas# we# dqm addr i/os command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) ( 3) l l h h x bank/row x read (select bank and column, and start read burst) (4) l h l h l/h 8 bank/col x write (select bank and column, and start write burst) (4) l h l l l/h 8 bank/col valid burst terminate l h h l x x active precharge (deactivate row in bank or banks) ( 5) l l h l x code x auto refresh or self refresh (enter self refresh mode) (6, 7) l l l h x x x load mode register (2) l l l l x op-code x write enable/output enable (8) CCCCl C active write inhibit/output high-z (8) CCCC h C high-z register de? ni tion sec tion. the load mode register command can only be issued when all banks are idle, and a sub se quent ex e cut able com mand cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs se lects the bank, and the address pro vid ed on inputs a0-12 selects the row. this row remains active (or open) for ac cess es until a precharge com mand is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-9 se lects the starting column location. the value on input a10 de ter mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent ac cess es. read data appears commands the truth table provides a quick reference of available com mands. this is followed by a written de scrip tion of each com mand. three additional truth tables appear following the op er a tion section; these tables provide current state/ next state information. command inhibit the command inhibit function pre vents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively de se lect ed. op er a tions already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this pre vents unwanted commands from being registered dur ing idle or wait states. op er a tions already in progress are not affected. load mode register the mode register is loaded via inputs a0-11 (a12 should be driven low). see mode reg is ter heading in the notes: 1. cke is high for all commands shown except self refresh. 2. a0-11 de? ne the op-code written to the mode register and a12 should be driven low. 3. a0-12 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-9 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are dont care. 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the i/os during writes (zero-clock delay) and reads (two-clock delay).
8 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com on the i/os sub ject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the cor re spond ing i/os will be high-z two clocks later; if the dqm signal was registered low, the i/os will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-9 se lects the starting column location. the value on input a10 de ter mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for sub se quent accesses. input data appearing on the i/os is written to the memory array subject to the dqm input logic level ap pear ing co in ci dent with the data. if a given dqm signal is registered low, the cor re spond ing data will be written to memory; if the dqm signal is registered high, the cor re spond ing data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a speci? ed time (trp) after the precharge command is is sued. input a10 determines wheth er one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. oth er wise ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated pri or to any read or write commands being is sued to that bank. auto precharge auto precharge is a feature which performs the same in di vid u al-bank precharge function de scribed above, with out re quir ing an explicit command. this is ac com plished by using a10 to enable auto precharge in conjunction with a spe ci? c read or write command. a precharge of the bank/row that is ad dressed with the read or write com mand is au to mat i cal ly performed upon com ple tion of the read or write burst, except in the full-page burst mode, where auto precharge does not ap ply. auto precharge is non per sis tent in that it is either enabled or disabled for each in di vid u al read or write com mand. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not is sue another command to the same bank until the precharge time (t rp ) is completed. this is determined as if an explicit precharge com mand was issued at the earliest possible time. burst terminate the burst terminate command is used to truncate either ? xed-length or full-page bursts. the most recently reg is tered read or write command prior to the burst ter mi nate command will be truncated. auto refresh auto refresh is used during normal op er a tion of the sdram and is analagous to cas#-before-ras# (cbr) re fresh in con ven tion al drams. this com mand is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh con trol ler. this makes the address bits dont care during an auto re fresh command. each 512mb sdram requires 8,192 auto re fresh cycles every refresh period (t ref ). pro vid ing a dis trib ut ed auto re fresh command will meet the refresh re quire ment and ensure that each row is re freshed. al ter na tive ly, 8,192 auto re fresh com mands can be is sued in a burst at the minimum cycle rate (t rc ), once every refresh period (t ref ). self refresh* the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data with out external clocking. the self re fresh command is ini ti at ed like an auto refresh com mand except cke is dis abled (low). once the self re fresh command is reg is tered, all the inputs to the sdram become dont care, with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to tras and may remain in self refresh mode for an inde? nite period beyond that. * self refresh available in commercial and industrial tem per a tures only.
9 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com absolute maximum ratings parameter unit voltage on v cc , v ccq supply relative to vss -1 to 4.6 v voltage on nc or i/o pins relative to vss -1 to 4.6 v operating temperature ta (mil) -55 to +125 c operating temperature ta (ind) -40 to +85 c storage temperature, plastic -55 to +125 c note: stress greater than those listed under "absolute maximum ratings" may cause per ma nent damage to the device. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this speci? cation i s not implied. exposure to ab so lute maximum rating con di tions for extended periods may affect reliability. capacitance (note 2) parameter symbol max unit input capacitance: clk ci1 9 pf addresses, ba0-1 input capacitance ca 34 pf input capacitance: all other input-only pins ci2 12 pf input/output capacitance: i/os cio 12 pf bga thermal resistance description symbol max unit notes junction to ambient (no air? ow) theta ja 13.9 c/w 1 junction to ball theta jb 10.3 c/w 1 junction to case (top) theta jc 4.6 c/w 1 note: refer to application note pbga thermal resistance correlation at www.wedc.com in the application notes section for mod eling conditions. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is de? ned as a signal cycling within timing con straints spec i fied for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands is sued (a minimum of two clocks) for t xsr , because time is required for the com ple tion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh com mands must be issued as both self refresh and auto refresh utilize the row refresh counter.
10 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com dc electrical characteristics and operating conditions (notes 1, 6) v cc , v ccq = +3.3v 0.3v; -55c t a +125c parameter/condition symbol min max units supply voltage v cc ,v ccq 3 3.6 v input high voltage: logic 1; all inputs (21) v ih 2 v cc + 0.3 v input low voltage: logic 0; all inputs (21) v il -0.3 0.8 v input leakage current: any input 0v v in v cc (all other pins not under test = 0v) i i -5 5 a input leakage address current (all other pins not under test = 0v) i i -25 25 a output leakage current: i/os are disabled; 0v v out v ccq i oz -5 5 a output levels: output high voltage (i out = -4ma) output low voltage (i out = 4ma) v oh 2.4 C v v ol C 0.4 v icc specifications and conditions (notes 1,6,11,13) v cc , v ccq = +3.3v 0.3v; -55c t a +125c parameter/condition symbol max units operating current: active mode; burst = 2; read or write; t rc = t rc (min); cas latency = 3 (3, 18, 19) i cc1 550 ma standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress (3, 12, 19) i cc3 225 ma operating current: burst mode; continuous burst; read or write; all banks active; cas latency = 3 (3, 18, 19) i cc4 575 ma self refresh current: cke 0.2v (27) i cc7 30 ma
11 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com parameter symbol -100 -125 -133 unit min max min max min max access time from clk (pos. edge) cl = 3 t ac 7 6 5.5 ns cl = 2 t ac 766ns address hold time t ah 1 1 0.8 ns address setup time t as 221.5ns clk high-level width t ch 332.5ns clk low-level width t cl 332.5ns clock cycle time (22) cl = 3 t ck 10 8 7.5 ns cl = 2 t ck 13 10 10 ns cke hold time t ckh 1 1 0.8 ns cke setup time t cks 221.5ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 0.8 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 2 1.5 ns data-in hold time t dh 1 1 0.8 ns data-in setup time t ds 221.5ns data-out high-impedance time cl = 3 (10) t hz 765.5ns cl = 2 (10) t hz 766ns data-out low-impedance time t lz 1 1 1 ns data-out hold time (load) (26) t oh 3 3 3 ns data-out hold time (no load) t ohn 1.8 1.8 1.8 ns active to precharge command t ras 50 120,000 50 120,000 50 120,000 ns active to active command period t rc 70 68 68 ns active to read or write delay t rcd 20 20 20 ns refresh period (8,192 rows) C commercial, industrial t ref 64 64 64 ms refresh period (8,192 rows) C military t ref 16 16 16 ms auto refresh period t rfc 70 70 70 ns precharge command period t rp 20 20 20 ns active bank a to active bank b command t rrd 20 20 20 ns transition time (7) t t 0.3 1.2 0.3 1.2 0.3 1.2 ns write recovery time (23) t wr 1 clk + 7ns 1 clk + 7ns 1 clk + 7.5ns (24) 15 15 15 ns exit self refresh to active command t xsr 80 80 75 ns electrical characteristics and recommended ac operating characteristics (notes 5, 6, 8, 9, 11)
12 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com ac functional characteristics (notes 5,6,7,8,9,11) parameter/condition symbol -100 -125 -133 units read/write command to read/write command (17) t ccd 111t ck cke to clock disable or power-down entry mode (14) t cked 1 1 1 t ck cke to clock enable or power-down exit setup mode (14) t ped 111t ck dqm to input data delay (17) t dqd 0 0 0 t ck dqm to data mask during writes t dqm 0 0 0 t ck dqm to data high-impedance during reads t dqz 2 2 2 t ck write command to input data delay (17) t dwd 0 0 0 t ck data-in to active command (15) t dal 455t ck data-in to precharge command (16) t dpl 2 2 2 t ck last data-in to burst stop command (17) t bdl 111t ck last data-in to new read/write command (17) t cdl 1 1 1 t ck last data-in to precharge command (16) t rdl 2 2 2 t ck load mode register command to active or refresh command (25) t mrd 222t ck data-out to high-impedance from precharge command (17) cl = 3 t roh 333t ck cl = 2 t roh 2t ck notes: 1. all voltages referenced to v ss . 2. this parameter is not tested but guaranteed by design. f = 1 mhz, t a = 25c. 3. i cc is dependent on output loading and cycle rates. speci? ed values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum speci? cations are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc and v ccq must be powered up simultaneously.) the two auto refresh command wake- ups should be repeated any time the t ref refresh re quire ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate speci? cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: q 1.5v 50? 10. t hz de? nes the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i cc spec i ? ca tions are tested after the device is properly initialized. 14. timing actually speci? ed by t cks ; clock(s) speci? ed as a reference only at minimum cycle rate. 15. timing actually speci? ed by t wr plus t rp ; clock(s) speci? ed as a reference only at minimum cycle rate. 16. timing actually speci? ed by t wr . 17. required clocks are speci? ed by jedec functionality and are not de pen dent on any timing parameter. 18. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. v ih overshoot: v ih (max) = v ccq + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 22. the clock frequency must remain constant (stable clock is de? ned as a signal cycling within timing constraints speci? ed for the clock pin) during access or precharge states (read, write, including t wr , and precharge com mands). cke may be used to reduce the data rate. 23. auto precharge mode only. the precharge timing budget (t rp ) begins 7.5ns/7ns after the ? rst clock delay, after the last write is executed. 24. precharge mode only. 25. jedec and pc100 specify three clocks. 26. parameter guaranteed by design. 27. self refresh available in commercial and industrial temperatures only.
13 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com package dimension: 219 plastic ball grid array (pbga) all linear dimensions are millimeters and parenthetically in inches bottom view 32.1 (1.264) max 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t r p n m l k j h g f e d c b a 25.1 (0.988) max 19.05 (0.750) nom 1.27 (0.050) nom 19.05 (0.750) nom 2.03 (0.080) max 0.61 (0.024) nom 219 x ? 0.762 (0.030) nom
14 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com ordering information white electronic designs corp. sdram configuration, 32m x 72 3.3v power supply frequency (mhz) 100 = 100mhz 125 = 125mhz 133 = 133mhz package: b = 219 plastic ball grid array (pbga), 32mm x 25mm device grade: m = mil i tary -55c to +125c i = in dus tri al -40c to +85c c = com mer cial 0c to +70c w 3 32m 72 v - xxx b x
15 white electronic designs w332m72v-xbx march 2006 rev. 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com document title 32mx72 sdram multi-chip package, 32mm x 25mm, 219 pbga revision history rev # history release date status rev 0 initial release april 2004 advanced rev 1 changes (pg. 1, 6, 9, 10, 11, 12, 14, 15) 1.1 change weight to 3.5g typical 1.2 change status to final 1.3 add 133mhz speed grade option 1.4 update capacitance data table 1.5 changes max storage temperature to 125c 1.6 add thermal resistance values 1.7 update i cc1 , i cc3 , i cc4 and i cc7 values june 2005 final rev 2 changes (pg. 1, 11, 15) 2.1 update ac timing parameters august 2005 final rev 3 changes (pg. 1, 2, 15) 2.1 change ball e5, e10, f5, l12 and k5 from nc to dnu march 2006 final

▲Up To Search▲

Price & Availability of W332M72V-133SBI

	To Download W332M72V-133SBI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .